Embodiments of the present invention relate to a static random access memory (SRAM) and particularly to power reduction in a standby mode of operation.
Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit processing. In particular, a balance between high packing density and yield requires a finely tuned manufacturing process. Minimum feature sizes of high density memory cells are frequently less than corresponding feature sizes of peripheral circuits. These minimum feature sizes often result in undesirable current leakage in the memory cell during both active and standby modes of operation. Ma et al. (U.S. Pat. No. 6,560,139) disclose such an undesirable leakage path. Referring to FIG. 1, there is a six transistor (6T) SRAM cell of the prior art as disclosed by Ma et al. The 6T cell includes a first inverter formed by p-channel transistor P1 and n-channel transistor N1. The first inverter is cross-coupled with a second inverter formed by p-channel transistor P2 and n-channel transistor N2. Access transistors 100 and 102 couple the memory cell to bit line (BL) and complementary bit line (/BL), respectively, when the word line (WL) is high. When the word line is low, there are two primary subthreshold leakage paths 104 and 106 in the memory cell for the illustrated data state. Leakage path 104 is through access transistor 100 to the “0” state terminal of the memory cell. Leakage path 106 is from the “1” state terminal of the memory cell through n-channel transistor N2. Ma et al. disclose the subthreshold drain current is an exponential function of Vgs-Vt, where Vgs is the gate-to-source voltage and Vt is the threshold voltage of the respective n-channel transistor. Ma et al. further disclose that the magnitude of read current when the word line is high is essentially the saturation current of n-channel transistor 100, and that this saturation current is proportional to a square of the difference between Vcc and Vt. Therefore, the read current declines faster than the leakage current as the supply voltage (Vcc) is lowered. (col. 2, lines 35-49). Ma et al. have recognized these problems and have used both small 301A and large 303A bias transistors for memory cells of an array having a high word line and only a small bias transistor 301B for memory cells of the array having a low word line. (FIG. 3, col. 3, lines 41-55). Ma et al., however, have not addressed problems that arise with multiple subarrays and for active and standby modes of operation.